The present invention relates to a semiconductor memory device, more specifically to a semiconductor memory device and a method for fabricating the same which can fabricate a DRAM (Dynamic Random Access Memory) of high integration and high efficiency at low costs.
A DRAM is a semiconductor device which may comprise one transistor and one capacitor, and its structures and methods for fabricating the structures have been conventionally studied for fabricating semiconductor devices of high density, high integration and high efficiency.
To achieve higher integration of a DRAM, it is effective to make the capacitor area smaller. The capacitance reduction accompanies soft error resistance degradation. This is a disadvantage. Lower electric power consumption of the device as well as higher integration has achieved, but the electric power consumption reduction makes the junction capacitance of the device more influential, which is a barrier to higher speed operation of the device.
As effective means to solve these disadvantages, a method for fabricating a DRAM using an SOI (Semiconductor On Insulator) substrate in place of the conventional silicon substrate has been proposed.
By applying the SOI structure to a DRAM, perfect isolation between devices can be made possible, and the soft error immunity and latch-up resistance can be much improved. The junction area can be reduced, and high speed operation at low electric power consumption can be made possible. Furthermore, the soft error immunity can be thus improved, which allows a smaller capacitance. The capacitor forming process can be accordingly simplified.
Also proposed has been the so-called bonded SOI technique in which another substrate is adhered to a surface of a silicon substrate with an insulating portion formed on, which is on the side of the insulating portion, and the silicon substrate is polished to form a semiconductor layer on the insulating portion. A DRAM using this bonded SOI technique is disclosed in Japanese Patent Laid-Open Publication No. Tokkaihei 04-225276/1992 and Japanese Patent Laid-Open Publication No. Tokkaihei 06-104410/1994.
The DRAM using the above-described conventional SOI structure can simplify the capacitor forming process to thereby decrease costs, but cost increase due to the use of the SOI structure exceeds the cost decrease, sometimes with the result of higher fabrication costs.
In devices using the above-described conventional SOI structure, the devices are fabricated after the SOI substrate is formed. The substrate is subjected to all heat treatments for forming the devices. Because SOI substrates are usually more susceptible of heat treatments than the usual substrates, the wafers are easily deformed, and crystal defects are easily introduced. As a result, the fabrication yields are often low.
In the DRAM using the above-described SOI structure, for the purpose of reducing this disadvantage as much as possible, a material having a thermal diffusion coefficient equal to that of the SOI layer supported on the support substrate, e.g., a semiconductor substrate of the same single crystal as the SOI layer, must be used. This often adds to fabrication costs of the DRAM.
In the bonded SOI, devices are formed on the SOI layer which is adhered thereto the substrate and polished. Accordingly it is necessary to finish the polished surface in a speculum of high precision. The polishing step often adds to fabrication costs.
To form the usual SOI substrate, the polishing step of planarizing a surface of a semiconductor substrate before the substrate is adhered to, and the polishing step of polishing the adhered semiconductor substrate to a thin film to form the SOI layer are necessary. This often adds to fabrication costs.
The use of the SOI structure makes it difficult to apply back bias to the channel regions of transistors, and the source-drain voltage resistance is often degraded due to charges accumulated in the back gates.
To prevent erroneous operation of memories, it is effective to cover the bit lines with shield electrodes. In the conventional DRAM structure, however, a number of lines and capacitors are formed on the bit line, which makes it difficult to cover the bit lines with the shield electrodes.
The above-described disadvantages make it difficult to form memories of high soft error immunity and reliability, which makes it accordingly difficult to reduce the capacitance to thereby simplify the fabrication process.
An object of the present invention is to provide a semiconductor memory device structure which permits a semiconductor memory device including the SOI structure to be fabricated at low costs without fabrication yield decrease, and a method for fabricating the same.
The above-described object is achieved by a semiconductor memory device comprising: a silicon layer having a first diffused region and a second diffused region formed therein; a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions; a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region; and a bit line formed on the other side of the silicon layer and connected to the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated.
The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure, etc. of the capacitor. Short circuit between the capacitor and the bit line can be prevented.
The above-described object is also achieved by a semiconductor memory device comprising: a silicon layer having a first diffused region and a second diffused region formed therein; a gate electrode formed through an insulating film on one side of the silicon layer between the first and the second diffused regions; a capacitor formed on said one side of the silicon layer and having a storage electrode connected to the first diffused region; a bit line formed on said one side of the silicon layer and connected to the second diffused region; and a strapping word line formed on the other side of the silicon layer and connected to the gate electrode, whereby a semiconductor memory device of SOI structure can be easily fabricated.
In the above-described semiconductor memory device it is preferable that a connection surface of the storage electrode, which are connected to the first diffused region, is substantially parallel with a surface of the storage electrode, which correspond to the connection surface, whereby a DRAM process and an SOI process can be easily unified.
The object of the present invention can be achieved by the semiconductor memory device comprising a semiconductor memory device comprising: a device layer including a semiconductor layer having a first diffused region and a second diffused region formed therein, a transistor having a gate electrode formed through an insulation film on one side of the semiconductor layer between the first and the second diffused regions, and a capacitor formed on said one side of the semiconductor layer and having a storage electrode connected to the first diffused region; a bit line formed on the other side of the semiconductor layer, and extended in a direction normal to the gate electrode; and a support substrate formed on said one side of the semiconductor layer for supporting the device layer; the semiconductor layer including a first region which is extended in the direction of extension of the bit line and includes the first diffused region and the second diffused region, and a second region which is extended in a direction of extension of the gate electrode in the first region and includes the second diffused region; a first contact hole being formed in the first region for connecting the first diffused region to the capacitor; and a second contact hole being formed in the second region for connecting the bit line with the second diffused region, whereby a semiconductor memory device of SOI structure can be easily fabricated.
The bit line connected to the second diffused region is formed on the other side of the semiconductor layer, whereby the bit line can be arranged without restriction by the structure of the capacitor, etc. Short circuit between the capacitor and the bit line can be prevented.
The second contact hole for connecting the bit line with the second diffused region is formed in the second region of the semiconductor layer, whereby the bit line can be connected, spaced from the channel region of the transistor. Even if disalignment takes place in opening the contact hole for the bit line, connection of the bit line with the channel region can be prevented.
In the above-described semiconductor memory device it is preferable that the first region and the second region are connected with each other, whereby connection between the bit line and the channel region can be prevented without adding to the number of fabrication steps.
In the above-described semiconductor memory device it is preferable that the second diffused region in the first region and the second diffused region in the second region are formed spaced from each other.
In the above-described semiconductor memory device it is preferable that the semiconductor memory device further comprises a first wiring layer formed on said one side of the semiconductor layer for connecting the first and the second regions with each other, whereby even in a case that the diffused region resistance between the second diffused region and the bit line increases, connection resistance between the second diffused region and the bit line can be compensated.
In the above-described semiconductor memory device it is preferable that the semiconductor memory device further comprises a strapping word line formed on said other side of the semiconductor layer and connected to the gate electrode, whereby the strapping word line can be easily formed without restriction by the structure of the capacitor, etc.
In the above-described semiconductor memory device it is preferable that the semiconductor memory device further comprises a strapping word line formed on said one side of the semiconductor layer and connected to the gate electrode.
In the above-described semiconductor memory device it is preferable that the semiconductor memory device further comprises a shield electrode formed on the bit line for suppressing interference between the bit lines, whereby noise on the bit line is removed, and interference between the adjacent bit lines can be suppressed.
In the above-described semiconductor memory device it is preferable that the semiconductor memory device further comprises a second wiring layer formed on said the other side of the semiconductor layer and electrically connected to a region of the semiconductor layer between the first and the second diffused regions, whereby charges accumulated in the region of the semiconductor layer between the first and the second diffused regions are released for potential stabilization, and the transistor can have improved reliability.
In the above-described semiconductor memory device it is preferable that the bit line is electrically connected to a region of the semiconductor layer between the first and the second diffused regions, whereby charges accumulated in the region of the semiconductor layer between the first and the second diffused regions are released for potential stabilization.
The object of the present invention can be achieved by a method for fabricating a semiconductor memory device comprising: a gate electrode forming step of forming a gate electrode on one side of a semiconductor substrate; a diffused region forming step of implanting an impurity into the semiconductor substrate with the gate electrode as a mask to form a first diffused region and a second diffused region; a capacitor forming step of forming a capacitor having a storage electrode connected to the first diffused region on the semiconductor substrate with the first and the second diffused regions formed therein; a support substrate forming step of forming a support substrate on the semiconductor substrate with the capacitor formed thereon; and a semiconductor layer forming step of removing the semiconductor substrate at the other side of the semiconductor substrate until bottoms of the second and the first diffused regions are exposed, to form a semiconductor layer, whereby the planarization step of the SOI process and the planarization step of the DRAM process can be rationalized, and fabrication cost reduction is possible.
The capacitor is formed before the substrate is adhered, whereby no high-temperature heat treatment is necessary after the adhesion of the substrate. Accordingly no wafer deformation nor crystal defects are introduced by the high-temperature heat treatment, and fabrication yields can be improved.
In the above-described method for fabricating the semiconductor memory device it is preferable that the method further comprises, after the semiconductor layer forming step, a bit line forming step of forming a bit line connected to the second diffused region, whereby the contact hole for the bit line can be made shallower, and formation of the contact hole can be much simplified.
The bit line can be arranged without restriction by the structure of the capacitor, etc. while short-circuit between the capacitor and the bit line can be prevented. The capacitor and the bit line can be independently located from each other, whereby higher integration can be obtained.
In the above-described method for fabricating the semiconductor memory device, it is preferable that the method further comprises, after the bit line forming step, a shield electrode forming step of forming a shield electrode for suppressing interference between the bit lines.
In the above-described method for fabricating the semiconductor memory device, it is preferable that the method further comprises, after the diffused region forming step and before the bit line forming step, a wiring layer forming step of forming a wiring layer for reducing connection resistance between the bit line and the second diffused region.
In the above-described method for fabricating the semiconductor memory device, it is preferable that the method further comprises, after the diffused region forming step and before the support substrate forming step, a bit line forming step of forming a bit line connected to the second diffused region.
In the above-described method for fabricating the semiconductor memory device, it is preferable that the method further comprises, after the semiconductor layer forming step, a strapping word line forming step of forming a strapping word line connected to the gate electrode.
In the above-described method for fabricating the semiconductor memory device, it is preferable that the method further comprises, after the diffused region forming step, a strapping word line forming step of forming a strapping word line connected to the gate electrode.
In the above-described method for fabricating the semiconductor memory device, it is preferable that after the semiconductor layer forming step, the semiconductor layer except the device region is removed, whereby the semiconductor memory device can be fabricated without forming a device isolation film. Accordingly cell area increase due to birds beaks can be reduced, and the semiconductor memory device can have higher integration.
In the above-described method for fabricating the semiconductor memory device it is preferable that after the semiconductor layer forming step, an impurity of a conduction type different from that of the second and the first diffused regions is doped in a region of the semiconductor layer where no active element is formed, whereby the semiconductor memory device can have higher integration because of device isolation by p-n junction.
In the above-described method for fabricating the semiconductor memory device it is preferable that the method further comprises, before the gate electrode forming step, a device isolation film forming step of forming on said one side of the semiconductor substrate a device isolation film which defines a device region; and in the semiconductor layer forming step the semiconductor substrate is removed at said other side of the semiconductor substrate until a bottom of the device isolation film is exposed, whereby the device isolation film can be used as the stopper, and the semiconductor layer can be easily formed.
In the above-described method for fabricating the semiconductor memory device it is preferable that the method further comprises, before the gate electrode forming step, a device isolation film forming step of forming on said one side of the semiconductor substrate a device isolation film which defines a device region; in the device isolation film forming step, the device region including a first region which is extended in a direction of extension of the bit line and includes the first and the second diffused regions, and a second region which is extended in a direction of extension of the gate electrode in the first region and includes the second diffused region, is formed; in the capacitor forming step the first diffused region is connected with the capacitor in the first region; in the semiconductor forming step the semiconductor substrate is removed at said other side of the semiconductor substrate until a bottom of the device isolation film is exposed; and in the bit line forming step the bit line is connected with the second diffused region in the second region, whereby the bit line can be connected spaced from the channel region, and even if disalignment takes place in forming the opening for the bit line, connection between the bit line and the channel region can be prevented.
In the above-described method for fabricating the semiconductor memory device it is preferable that the method further comprises, the method further comprises, before the gate electrode forming step, a device isolation film forming step of forming on said one side of the semiconductor substrate a device isolation film which defines a device region, and a opening forming step of removing the device isolation film in the first region of the device isolation film to form an opening; the method further comprises, after the semiconductor layer forming step, a strapping word line forming step of forming a strapping word line connected to the gate electrode; in the gate electrode forming step the gate electrode extended in the first region is formed buried in the opening; and in the strapping word line forming step the strapping word line is connected with the gate electrode in the first region, whereby the gate electrodes and the strapping word lines can be easily connected with each other.
The above-described object can be achieved by a method for fabricating a semiconductor memory device comprising a device isolation film forming step of forming a device isolation film on one side of a semiconductor layer, a semiconductor device forming step of forming a semiconductor device on the semiconductor substrate with the device isolation film formed on, and a semiconductor layer forming step of forming a semiconductor layer, in a case that the device isolation film includes a first device isolation film having a first film thickness and a second device isolation film having a second film thickness which is smaller than the first film thickness, the semiconductor layer forming step comprising the steps of polishing the semiconductor substrate until the first device isolation film is exposed, etching the exposed first device isolation film so that the first device isolation film and the second device isolation film have substantially the same film thickness, and polishing the semiconductor substrate until the second device isolation film is exposed.